In a compound semiconductor device, particularly in a super-high frequency device such as a high electron mobility transistor (HEMT) including an arsenide semiconductor layer over a substrate such as an InP substrate, higher frequency has been trying to be enabled by reducing a gate intrinsic capacitance or a gate parasitic capacitance. As a way to reduce a gate intrinsic capacitance, shortening of a gate length is cited. As a way to reduce a gate parasitic capacitance, it is cited to form a cavity at an interlayer insulating film at a periphery of a gate, and to use an air bridge wiring structure without forming an interlayer insulating film at a periphery of a gate.
However, it is difficult to further improve output characteristics such as a gain by these conventional HEMTs.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2011-249439    [Patent Document 2] Japanese National Publication of International Patent Application No. 2008-533717